1. Field of the Invention
This invention relates to a charge pump circuit for generating a voltage V.sub.BB for a semiconductor memory device.
2. Description of the Prior Art
A charge pump circuit such as shown in FIG. 2 is used as a V.sub.BB power source for supplying a voltage V.sub.BB to a semiconductor substrate of a semiconductor memory device. The charge pump circuit serves to pump electric charges from the semiconductor substrate to the ground so as to set the potential of the semiconductor substrate at a level under the ground potential level.
In this charge pump circuit, first a terminal 11 is set to active (LOW level) so that a P-MOS transistor Q.sub.11 is turned on, and consequently the potential of node 13 increases to the V.sub.CC level due to the coupling effect of a pumping capacitor C.sub.11. As a result, an N-MOS transistor Q.sub.13 is turned on, and consequently the potential of the node 13 decreases to the ground level. Accordingly, the pumping capacitor C.sub.11 is charged by the V.sub.CC power source.
Then, the terminal 11 is returned to HIGH level and a terminal 12 is set to active (HIGH level) so that an N-MOS transistor Q.sub.12 is turned on. This causes the potential of the first terminal of the pumping capacitor C.sub.11 to switch from the V.sub.CC level to the GND level, whereby the node 13 corresponding to the other terminal of the pumping capacitor C.sub.11 is pulled down to a level lower than the GND level by the coupling effect of the capacitor C.sub.11. Accordingly, the N-MOS transistor Q.sub.13 is turned off, and an N-MOS transistor Q.sub.14 is turned on, thereby supplying the voltage V.sub.BB to a semiconductor substrate of a semiconductor memory device. In other words, the charge pump circuit absorbs the electric charges from the substrate so that the potential of the substrate is reduced to the V.sub.BB level.
In the above prior art circuit, when the P-MOS transistor Q.sub.11 is turned on, a decrease in the potential level of the node 13 after the activation of the N-MOS transistor Q.sub.13 causes the N-MOS transistor Q.sub.13 to turn off. As a result, the potential level of the node 13 cannot decrease to a level less than the threshold voltage V.sub.th of the transistor Q.sub.13. Therefore, the charging level of the pumping capacitor C.sub.11 cannot reach the level of the V.sub.CC power source, and is lower than this level by about the threshold voltage V.sub.th.
In contrast, when the N-MOS transistor Q.sub.12 is turned on, the N-MOS transistor Q.sub.14 remains in the on state as long as the level of the node 13 is lower than the voltage V.sub.BB by about the threshold voltage V.sub.th of the N-MOS transistor Q.sub.14. Therefore, even when the level of the node 13 is pulled down to the level of (-V.sub.CC +V.sub.th), the resulting value of the voltage V.sub.BB is higher than this level by about the threshold voltage V.sub.th.
As a result, in such a prior art circuit, there is a problem in that the voltage generated as the voltage V.sub.BB is at a level of about (-V.sub.CC +2 .times.V.sub.th) and cannot reach a sufficiently low level, particularly when the voltage of the V.sub.CC power source is low.